Что (кто) такое Chip Scale Packaging - определение

INTEGRATED CIRCUIT PACKAGE THAT IS NO OR BARELY LARGER THAN THE INTEGRATED CIRCUIT IT CONTAINS

Wafer level chip scale package; Chip-scale packaging; Chip Scale Packaging; LFCSP; Wafer Level Chip Scale Package; Chip Scale Package; WLCSP; Chip size package; Chip scale package; Chip-Scale Package

Chip Scale Packaging

<hardware> (CSP) A type of surface mount {integrated circuit} packaging that provides pre-speed-sorted, pre-tested and pre-packaged die without requiring special testing. An example is Motorola's Micro SMT packaging. See also: chip-on-board, flip chip, multichip module, known good die, ball grid array. ["Chip scale packaging gains at SMI. (Surface Mount International)", Bernard Levine, Electronic News (1991), Sept 4, 1995 v41 n2081 p1(2)]. (2006-08-14)

Packaging machinery

ANY MACHINE USED FOR PACKAGING

Packaging machine

Packaging machinery is used throughout all packaging operations, involving primary packages to distribution packs. This includes many packaging processes: fabrication, cleaning, filling, sealing, combining, labeling, overwrapping, palletizing.

https://en.wikipedia.org/wiki/Packaging_machinery

Sustainable packaging

SUSTAINABLE PACKAGING IS AN INTEGRAL PART OF THE 'CIRCULAR ECONOMY'. ECO-FRIENDLY PACKAGING USES RAW MATERIALS AND THEN RESTORES THEM TO THEIR ORIGINS, MINIMIZING WASTE OF PRECIOUS RESOURCES – LIKE WATER AND ENERGY – NECESSARY FOR THEIR PRODUCTION.

Sustainable Packaging Coalition; Packaging and the environment; Green packaging; Green Cell Foam; Biodegradable packing material; Sustainable Packaging

Sustainable packaging is the development and use of packaging which results in improved sustainability. This involves increased use of life cycle inventory (LCI) and life cycle assessment (LCA)

https://en.wikipedia.org/wiki/Sustainable_packaging

Википедия

Chip-scale package

A chip scale package or chip-scale package (CSP) is a type of integrated circuit package.

Originally, CSP was the acronym for chip-size packaging. Since only a few packages are chip size, the meaning of the acronym was adapted to chip-scale packaging. According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm.

The concept was first proposed by Junichi Kasai of Fujitsu and Gen Murakami of Hitachi Cable in 1993. The first concept demonstration however came from Mitsubishi Electric.

The die may be mounted on an interposer upon which pads or balls are formed, like with flip chip ball grid array (BGA) packaging, or the pads may be etched or printed directly onto the silicon wafer, resulting in a package very close to the size of the silicon die: such a package is called a wafer-level package (WLP) or a wafer-level chip-scale package (WL-CSP). WL-CSP had been in development since 1990s, and several companies begun volume production in early 2000, such as Advanced Semiconductor Engineering (ASE).

https://en.wikipedia.org/wiki/Chip-scale package